xvredp

Vector Reciprocal Estimate Double-Precision

xvredp XT,XB

A double-precision floating-point estimate of the reciprocal of src is placed into doubleword element i of VSR[XT] in double-precision format.

Encoding

Binary Layout

Format XX2-form

Opcode 0xF0000368

Extension VSX

Operands

XT
Target Vector Register
XB
Source Vector Register

Example

xvredp vs1, vs3

Registers Altered

FPSCR FX OX UX ZX VXSNAN

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Unless the reciprocal of src would be a zero, an infinity, or a QNaN, the estimate has a relative error in precision no greater than one part in 16384 of the reciprocal of src.

Operation

if MSR.VSX=0 then VSX_Unavailable()

reset_xflags()
vresult = bfp_RECIPROCAL_ESTIMATE(VSR[32×BX+B].dword[i])
rnd = bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, vresult)
vresult.word[i] = bfp64_CONVERT_FROM_BFP(rnd)

if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if zx_flag=1 then SetFX(FPSCR.ZX)
ex_flag = ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.ZE & zx_flag)

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

The xvredp instruction is used to estimate the reciprocal of a double-precision floating-point number with high precision. It's important to ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. Developers should also handle exceptions by checking the FPSCR flags for overflow (OX), underflow (UX), zero divide (ZX), and invalid operation (VXSNAN).