xvtdivsp

VSX Vector Test for software Divide Single-Precision XX3-form

xvtdivsp BF,XA,XB

Performs a vectorized single-precision floating-point division test.

Details

The xvtdivsp instruction performs a vectorized single-precision floating-point division test on the elements of two VSX registers, XA and XB, and sets flags based on the results.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
end
eq_flag ←0b0
gt_flag ←0b0
for i = 0 to 3 do
    src1 ←VSR[32×AX+A].word[i]
    e_a ←src1.bit[1:8] - 127
    src2 ←VSR[32×BX+B].word[i]
    e_b ←src2.bit[1:8] - 127
    fe_flag is set to 1 for any of the following conditions.
        – src1 is a NaN or an infinity.
        – src2 is a zero, a NaN, or an infinity.
        – e_b is less than or equal to -126.
        – e_b is greater than or equal to 125.
        – src1 is not a zero and the difference, e_a - e_b, is greater than or equal to 127.
        – src1 is not a zero and the difference, e_a - e_b, is less than or equal to -125.
    fg_flag ←fg_flag |
               IsInf(src1) | IsInf(src2) |
               IsZero(src2) | IsDen(src2)
end
fl_flag ←xvredp_error() <= 2-14
CR.field[BF] ←0b1 || fg_flag || fe_flag || 0b0

Programming Note

The xvtdivsp instruction is used for vectorized single-precision floating-point division testing. It sets condition register flags based on the results of dividing elements from two VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction. Be cautious with NaNs, infinities, and zero values in the operands, as they can trigger special flag conditions. The instruction operates on 4-element vectors, so ensure proper alignment of data in the VSX registers.

Example

xvtdivsp cr0, vs2, vs3

Encoding

Binary Layout

Format XX3-form

Opcode 0xF00002E8

Extension VSX

Registers Altered CR field BF

Operands

BF
Condition Register Field
XA
Index for Source VSX Register A
XB
Index for Source VSX Register B