xvtdivsp

VSX Vector Test for software Divide Single-Precision XX3-form

xvtdivsp BF,XA,XB

Performs a vectorized single-precision floating-point division test.

Details

Tests whether a single-precision floating-point divide operation would be valid for each vector element and sets the specified condition register field based on the results. This VSX instruction examines operands in XA and XB (four single-precision values per 128-bit register) for division validity conditions such as divide-by-zero or invalid operands. The condition register field BF is updated to reflect test outcomes; no other state is modified.

Pseudocode Operation

for i in 0 to 3 do
  quotient_valid ← test_divide_conditions(XA[i], XB[i])
  CR[BF] ← (quotient_valid, 0, 0, 0)
end for

Programming Note

The xvtdivsp instruction is used for vectorized single-precision floating-point division testing. It sets condition register flags based on the results of dividing elements from two VSX registers. Ensure that the VSX facility is enabled (MSR.VSX=1) before using this instruction. Be cautious with NaNs, infinities, and zero values in the operands, as they can trigger special flag conditions. The instruction operates on 4-element vectors, so ensure proper alignment of data in the VSX registers.

Example

xvtdivsp cr0, vs2, vs3

Encoding

Binary Layout
18
0
BF
6
XA
16
XB
21
 
Format XX3-form
Opcode 0xF00002E8
Extension VSX
Registers Altered CR field BF

Operands

  • BF
    Condition Register Field
  • XA
    Index for Source VSX Register A
  • XB
    Index for Source VSX Register B