vmulhuw

Vector Multiply High Unsigned Word

vmulhuw vD, vA, vB

Multiplies unsigned words, returning the high 32 bits.

Details

The vmulhuw instruction multiplies each pair of unsigned 32-bit integers from the source vectors VSR[VRA+32] and VSR[VRB+32]. It places the high-order 32 bits of each 64-bit product into the corresponding word elements of the destination vector VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
   src1 ←EXTZ(VSR[VRA+32].word[i])
   src2 ←EXTZ(VSR[VRB+32].word[i])

   VSR[VRT+32].word[i] ←CHOP32((src1 × src2) >> 32)
end

Programming Note

The vmulhuw instruction is used for multiplying pairs of unsigned 32-bit integers from two source vectors and storing the high-order 32 bits of each product in a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vectors, so ensure proper alignment and ordering of data for accurate results.

Example

vmulhuw vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
648
21
 
Format VX-form
Opcode 0x10000288
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B