vmulhuw

Vector Multiply High Unsigned Word

vmulhuw vD, vA, vB

Multiplies unsigned words, returning the high 32 bits.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

648

21:31

 

Format VX-form

Opcode 0x10000289

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vmulhuw vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies each pair of unsigned 32-bit words from vA and vB, producing 64-bit products, and places the high 32 bits of each product into the corresponding 32-bit word of vD. Four independent word multiplications are performed. No condition register or status field modifications occur.

Operation

for i = 0 to 3 do
  product ← (vA[i*32:(i+1)*32]) × (vB[i*32:(i+1)*32])
  vD[i*32:(i+1)*32] ← product[32:63]
end for

Programming Note

The vmulhuw instruction is used for multiplying pairs of unsigned 32-bit integers from two source vectors and storing the high-order 32 bits of each product in a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vectors, so ensure proper alignment and ordering of data for accurate results.