xvsubsp

VSX Vector Subtract Single-Precision

xvsubsp XT, XA, XB

Subtracts the contents of two vector registers and places the result in another vector register.

Encoding

Binary Layout

110000

0:5

6:10

11:15

16:20

000000

21:28

000000

Format XX3-form

Opcode 0xF0000240

Extension VSX

Operands

XT
Target
XA
Src A
XB
Src B
VX
Target Vector Register

Example

xvsubsp vs1, vs2, vs3

Registers Altered

vxsnan_flag, vxisi_flag

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xvsubsp, each single-precision floating-point operand in word elements of VSR[XA] is negated and added to the corresponding element in VSR[XB]. The results are normalized and rounded to single precision before being placed into VSR[XT].

Operation

for i = 0 to 3 do
    src1 <- VSR[XA][i]
    src2 <- VSR[XB][i]
    if src1 is NaN or src2 is NaN then
        v <- Q(src1) or Q(src2)
        vxsnan_flag <- 1
    else if src1 is +Infinity and src2 is +Infinity then
        v <- +Infinity
        vxisi_flag <- 1
    else if src1 is -Infinity and src2 is -Infinity then
        v <- -Infinity
        vxisi_flag <- 1
    else if src1 is NZF and src2 is NZF then
        v <- S(src1, -src2)
    else if src1 is Zero and src2 is Zero then
        v <- Rezd
    else if src1 is +Zero and src2 is -Zero then
        v <- +Zero
    else if src1 is -Zero and src2 is +Zero then
        v <- -Zero
    else if src1 is NZF and src2 is Zero then
        v <- src1
    else if src1 is Zero and src2 is NZF then
        v <- -src2
    else if src1 is +Infinity and src2 is NZF then
        v <- +Infinity
    else if src1 is NZF and src2 is +Infinity then
        v <- -Infinity
    else if src1 is -Infinity and src2 is NZF then
        v <- -Infinity
    else if src1 is NZF and src2 is -Infinity then
        v <- +Infinity
    VSR[VX][i] <- v

Programming Note

The xvsubsp instruction performs element-wise subtraction of single-precision floating-point numbers in VSX registers. Be cautious with NaNs, infinities, and zeros as they can trigger special flags (vxsnan_flag, vxisi_flag) and may result in unexpected outcomes. Ensure that the input vectors are properly aligned to avoid alignment faults.