xxland

VSX Vector Logical AND

xxland XT, XA, XB

Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.

Encoding

Binary Layout

T

6:10

A

11:15

B

16:20

130

21:28

AX

29

BX

30

TX

31

 

Format XX3-form

Opcode 0xF0000410

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xxland vs1, vs2, vs3

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of VSR[XA] are ANDed with the contents of VSR[XB] and the result is placed into VSR[XT].

Operation

if MSR.VSX=0 then VSX_Unavailable()
VSR[32×TX+T] ← VSR[32×AX+A] & VSR[32×BX+B]

Programming Note

Ensure that the VSX (Vector Scalar Extensions) is enabled in the MSR register before using this instruction. The operation is performed on 128-bit vector registers, so both input and output must be properly aligned. This instruction operates at a high performance for bitwise operations on vectors.