xxland

VSX Vector Logical AND

xxland XT, XA, XB

Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.

Details

The contents of VSR[XA] are ANDed with the contents of VSR[XB] and the result is placed into VSR[XT].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
VSR[32×TX+T] ← VSR[32×AX+A] & VSR[32×BX+B]

Programming Note

Ensure that the VSX (Vector Scalar Extensions) is enabled in the MSR register before using this instruction. The operation is performed on 128-bit vector registers, so both input and output must be properly aligned. This instruction operates at a high performance for bitwise operations on vectors.

Example

xxland vs1, vs2, vs3

Encoding

Binary Layout
T
0
A
6
B
11
130
16
AX
21
BX
29
TX
30
 
Format XX3-form
Opcode 0xF00001B8
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B