xvmsubadp

VSX Vector Multiply-Subtract Type-A Double-Precision

xvmsubadp XT,XA,XB

Performs a double-precision floating-point multiply-subtract operation on vector elements.

Encoding

Binary Layout

1000

0:5

6:10

11:15

16:20

000000

21:28

000000

Format XX3-form

Opcode 0xF0000388

Extension VSX

Operands

XT
Target Vector Register
XA
Source Vector Register
XB
Source Vector Register

Example

xvmsubadp vs1, vs2, vs3

Registers Altered

FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a vector multiply-subtract operation on double-precision floating-point elements, computing XT = XT - (XA × XB) for each element. The operation is fused, rounding only once at the end. This instruction requires VSX support and updates FPSCR exception flags based on the operation results.

Operation

for i ∈ {0, 1}
  XT[i*64:(i+1)*64] ← XT[i*64:(i+1)*64] - (XA[i*64:(i+1)*64] × XB[i*64:(i+1)*64])
FPSCR ← update_exception_flags(FPSCR, results)

Programming Note

The xvmsubadp instruction is commonly used for complex floating-point arithmetic operations involving multiplication, subtraction, and addition. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, VXISI, OX, UX, and XX, which can be triggered by invalid operations or overflow conditions. The instruction operates on double-precision floating-point numbers and requires proper alignment of the input vectors.