xvmsubadp

VSX Vector Multiply-Subtract Type-A Double-Precision

xvmsubadp XT,XA,XB

Performs a double-precision floating-point multiply-subtract operation on vector elements.

Details

The xvmsubadp instruction performs the following operations: 1. Subtracts VSR[XB].dword[0] from VSR[XA].dword[0] 2. Multiplies the result by VSR[XT].dword[0] 3. Adds VSR[XT].dword[1] to the product 4. Stores the final result in VSR[XT].dword[0] The same operations are performed on VSR[XB].dword[1], VSR[XA].dword[1], and VSR[XT].dword[1], with the final result stored in VSR[XT].dword[1].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])
    src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    v   ←bfp_MULTIPLY_ADD(src1,src3,bfp_NEGATE(src2))
    rnd ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) |
                  (FPSCR.VE & vximz_flag) |
                  (FPSCR.VE & vxisi_flag) |
                  (FPSCR.OE & ox_flag) |
                  (FPSCR.UE & ux_flag) |
                  (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←result

Programming Note

The xvmsubadp instruction is commonly used for complex floating-point arithmetic operations involving multiplication, subtraction, and addition. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, VXISI, OX, UX, and XX, which can be triggered by invalid operations or overflow conditions. The instruction operates on double-precision floating-point numbers and requires proper alignment of the input vectors.

Example

xvmsubadp vs1, vs2, vs3

Encoding

Binary Layout

1000

000000

Format XX3-form

Opcode 0xF0000388

Extension VSX

Registers Altered FPSCR

Operands

XT
Target Vector Register
XA
Source Vector Register
XB
Source Vector Register