vor

Vector OR

vor vD, vA, vB

Bitwise OR of two 128-bit vectors.

Details

Performs a bitwise OR of two 128-bit vector registers and stores the result in a third vector register. Each bit position of the result is set if the corresponding bit in either input vector is set. No status flags are affected.

Pseudocode Operation

vD ← vA | vB

Programming Note

The vor instruction requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise a Vector Unavailable exception. Ensure that the vector registers involved are properly aligned and contain valid data for accurate results.

Example

vor vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1156
21
 
Format VX-form
Opcode 0x10000484
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B