vor

Vector OR

vor vD, vA, vB

Bitwise OR of two 128-bit vectors.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1156

21:31

 

Format VX-form

Opcode 0x10000484

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vor vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a bitwise OR of two 128-bit vector registers and stores the result in a third vector register. Each bit position of the result is set if the corresponding bit in either input vector is set. No status flags are affected.

Operation

vD ← vA | vB

Programming Note

The vor instruction requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise a Vector Unavailable exception. Ensure that the vector registers involved are properly aligned and contain valid data for accurate results.