mulhwu

Multiply High Word Unsigned

mulhwu RT, RA, RB

Multiplies two 32-bit integers and returns the upper 32 bits (Unsigned).

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

11

22:30

Rc

31

 

Format XO-form

Opcode 0x7C000016

Extension Base

Operands

• RT
  Target
• RA
  Src A
• RB
  Src B

Example

mulhwu r3, r4, r5

Registers Altered

CR0

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies two 32-bit unsigned integers (RA[32:63] and RB[32:63]) and stores the upper 32 bits of the 64-bit unsigned result in RT[32:63], with RT[0:31] undefined. If Rc=1, CR0 is updated based on the result.

Operation

prod ← (RA[32:63]) *u (RB[32:63]); RT[32:63] ← prod[32:63]; if Rc then CR0 ← (RT[32:63] < 0, RT[32:63] > 0, RT[32:63] = 0, SO)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.