ori
OR Immediate
ori RT,RS,SImm
Performs a bitwise OR operation between the contents of a register and an immediate value, placing the result in another register.
Encoding
Binary Layout
24
0:5
RS
6:10
RA
11:15
UI
16:31
Operands
-
RA
Target Register -
RS
Source Register -
UI
Unsigned 16-bit Immediate -
RT
Target General Purpose Register -
SImm
Sign-Extended 16-bit Immediate Value
Example
ori r3, r4, 0x1
// Set bit 0.
Related
Across architectures
No Operation : how x86, ARM, RISC-V, and PowerISA each do this.
More in Base
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
Performs a bitwise OR between a general-purpose register and a 16-bit unsigned immediate value, storing the result in another register. This is a base category instruction with no condition register or status updates.
Operation
RA ← RS | (0x0000 || UI)Extended Mnemonics
| Extended Mnemonic | Equivalent Instruction |
|---|---|
| nop | |
Programming Note
Warning: Other forms of ori Rx,Rx,0 that are not described in this section may also have micro-architectural effects on program execution. Use of these forms should be avoided except when software needs the associated micro-architectural effects.
Programming Note: This no-op is intended to be used by software for providing protection against the Spectre class of transient execution attacks by restricting eventually discarded out-of-order execution effects with transient register values, which may compromise confidential data via other covert channels.