pmxvf32gerpp
Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate
Performs a prefixed masked VSX vector 32-bit floating-point GER rank-1 update with positive multiply and positive accumulate.
Details
A prefixed MMA instruction that performs a masked rank-1 matrix update using 32-bit floating-point elements, with positive multiply (no sign flip) and positive accumulate semantics. The prefix word controls masking and additional configuration. This instruction requires MMA support and updates the accumulator register; no condition registers are directly modified by this operation.
Pseudocode Operation
Accumulator ← Accumulator + (masked_multiply_by_vsrX(XA) ⊗ masked_multiply_by_vsrY(XB))Programming Note
When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.