mtvsrqm

Move to VSR Quadword Mask VX-form

mtvsrqm VRT,RB

Moves a quadword mask from a general-purpose register to a vector scalar register.

Encoding

Binary Layout

0:5

VRT

6:10

11:15

1602

16:31

Format VX-form

Opcode 0x10140642

Extension VMX (AltiVec)

Operands

VRT
Target Vector Scalar Register
RB
Source General Purpose Register

Example

mtvsrqm v1, r5

Registers Altered

MSR, VSR[VRT+32]

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of GPR[RB] are used to determine the mask for VSR[VRT+32]. If bit 63 of GPR[RB] is 0, VSR[VRT+32] is set to all zeros. If bit 63 is 1, VSR[VRT+32] is set to all ones.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
else if GPR[RB].bit[63]=0 then
    VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000
else
    VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
end

Programming Note

This instruction sets the mask for a vector register based on the most significant bit of a general-purpose register. Ensure that the Vector Facility is enabled in the Machine State Register (MSR) before using this instruction; otherwise, it will raise an exception. The instruction does not require any specific alignment or ordering of operations.