vaddsws

Vector Add Signed Word Saturate

vaddsws vD, vA, vB

Adds 4 signed words with saturation.

Details

The vaddsws instruction performs a vectorized addition of signed words from two source vectors, saturating the result if it overflows. The operation is performed on each pair of corresponding elements in the source vectors, and the results are stored in the destination vector.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    sum ← src1 + src2
    if sum > 2^31 - 1 then
        VSR[VRT+32].word[i] ← 2^31 - 1
        SAT ← 1
    else if sum < -2^31 then
        VSR[VRT+32].word[i] ← -2^31
        SAT ← 1
    else
        VSR[VRT+32].word[i] ← sum
    end
end

Programming Note

The vaddsws instruction is useful for adding signed integers with overflow protection, ensuring that results do not exceed the bounds of a 32-bit signed integer. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious of potential performance overhead due to saturation checks, which can impact execution speed if many elements overflow.

Example

vaddsws vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
896
21
 
Format VX-form
Opcode 0x10000380
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B