vaddsws
Vector Add Signed Word Saturate
Adds 4 signed words with saturation.
Details
Adds each of four signed 32-bit words in vA to the corresponding word in vB, with saturation at the signed range [-2^31, 2^31-1]. Results are clamped to the valid signed 32-bit range; no status flags are affected.
Pseudocode Operation
for i in 0 to 3 do
sum ← SIGN_EXTEND(vA[i*32:(i+1)*32-1], 33) + SIGN_EXTEND(vB[i*32:(i+1)*32-1], 33)
if sum > 2147483647 then
vD[i*32:(i+1)*32-1] ← 2147483647
else if sum < -2147483648 then
vD[i*32:(i+1)*32-1] ← -2147483648
else
vD[i*32:(i+1)*32-1] ← sum[31:0]Programming Note
The vaddsws instruction is useful for adding signed integers with overflow protection, ensuring that results do not exceed the bounds of a 32-bit signed integer. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious of potential performance overhead due to saturation checks, which can impact execution speed if many elements overflow.
Example
Encoding
Operands
-
vD
Target -
vA
Src A -
vB
Src B