dcbt

Data Cache Block Touch

dcbt RA,RB,TH

Hints to the hardware to prefetch the cache block at the specified address into the cache.

Encoding

Binary Layout
0
GO
S
DEP
UNITCNT
T
U
ID
 
Format X-form
Opcode 0x7C00022C
Extension Base

Operands

  • TH
    Touch Hint (Stream ID)
  • RA
    Base Address
  • RB
    Index Address
  • EA
    Effective Address

Example

dcbt 0, 0, r3

// Prefetch data at r3.

Related

Across architectures

Cache Prefetch Hint : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Data cache prefetch hint that loads the cache block at effective address RA + RB into the data cache with streaming characteristics controlled by the TH field. Variants (dcbtt, dcbna, dcbtds) provide transient, non-allocating, and data stream hints. This is a memory hint with no side effects on registers or condition flags; the prefetch is advisory and may be ignored.

Operation

EA ← (RA) + (RB)
Prefetch_cache_block(EA, touch_hint=TH)

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
dcbt RA,RB dcbt RA,RB,0b00000
dcbtt RA,RB dcbt RA,RB,0b10000
dcbna RA,RB dcbt RA,RB,0b10001
dcbtds RA,RB,TH dcbt RA,RB,TH (TH=0b00000 or 0b01000-0b01111)

Programming Note

To maximize the utility of the Depth control mechanism, the architecture provides a hierarchy of three ways to program it. The DPFD field in the LPCR is used by the provisory/firmware to set a safe or appropriate default depth for unaware operating systems and applications. The DPFD field in the DSCR may be initialized by the aware OS and overwritten by an application via the OS-provided service when per stream control is unnecessary or unaffordable.