dcbt

Data Cache Block Touch

dcbt RA,RB,TH

dcbtt RA,RB

dcbna RA,RB

dcbtds RA,RB,TH

Hints to the hardware to prefetch the cache block at the specified address into the cache.

Details

The dcbt instruction provides a hint to the processor that the program will probably soon access all nascent load and store data streams associated with the specified stream ID. If GO=1 and S=0b00, the hint provided by the instruction is undefined.

Pseudocode Operation

if GO=1 and S=0b00 then
    undefined hint
else if GO=0 then
    no information provided by the instruction
else if GO=1 and S=0b10 then
    program will probably no longer access the data stream associated with the specified stream ID
else if GO=1 and S=0b11 then
    program will probably no longer access all nascent load and store data streams

Programming Note

To maximize the utility of the Depth control mechanism, the architecture provides a hierarchy of three ways to program it. The DPFD field in the LPCR is used by the provisory/firmware to set a safe or appropriate default depth for unaware operating systems and applications. The DPFD field in the DSCR may be initialized by the aware OS and overwritten by an application via the OS-provided service when per stream control is unnecessary or unaffordable.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
dcbtt
dcbna
dcbtds

Example

dcbt 0, 0, r3

Encoding

Binary Layout
0
0
GO
1
S
3
DEP
4
UNITCNT
57
T
58
U
59
ID
60
 
Format X-form
Opcode 0x7C00022C
Extension Base

Operands

  • TH
    Touch Hint (Stream ID)
  • RA
    Base Address
  • RB
    Index Address
  • EA
    Effective Address