dcbt

Data Cache Block Touch

dcbt RA,RB,TH

dcbtt RA,RB

dcbna RA,RB

dcbtds RA,RB,TH

Hints to the hardware to prefetch the cache block at the specified address into the cache.

Details

Data cache prefetch hint that loads the cache block at effective address RA + RB into the data cache with streaming characteristics controlled by the TH field. Variants (dcbtt, dcbna, dcbtds) provide transient, non-allocating, and data stream hints. This is a memory hint with no side effects on registers or condition flags; the prefetch is advisory and may be ignored.

Pseudocode Operation

EA ← (RA) + (RB)
Prefetch_cache_block(EA, touch_hint=TH)

Programming Note

To maximize the utility of the Depth control mechanism, the architecture provides a hierarchy of three ways to program it. The DPFD field in the LPCR is used by the provisory/firmware to set a safe or appropriate default depth for unaware operating systems and applications. The DPFD field in the DSCR may be initialized by the aware OS and overwritten by an application via the OS-provided service when per stream control is unnecessary or unaffordable.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
dcbtt
dcbna
dcbtds

Example

dcbt 0, 0, r3

// Prefetch data at r3.

Encoding

Binary Layout
0
0
GO
1
S
3
DEP
4
UNITCNT
57
T
58
U
59
ID
60
 
Format X-form
Opcode 0x7C00022C
Extension Base

Operands

  • TH
    Touch Hint (Stream ID)
  • RA
    Base Address
  • RB
    Index Address
  • EA
    Effective Address