xsmindp

VSX Scalar Minimum Double-Precision

xsmindp XT, XA, XB

Computes the minimum of two double-precision floating-point values and places the result into a vector scalar register.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

168

21:31

 

Format XX3-form

Opcode 0xF0000540

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xsmindp vs1, vs2, vs3

Registers Altered

FPSCR, VXSNAN

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares the double-precision floating-point value in XA with the value in XB and stores the minimum (or quiet NaN if either operand is NaN) in XT. Following IEEE 754 semantics, quiet NaNs propagate, and negative zero is considered less than positive zero. FPSCR is updated with the comparison result flags.

Operation

result ← DPFP_minimum(XA[0:63], XB[0:63])
XT[0:63] ← result
FPSCR ← update_fpscr(FPSCR, result)

Programming Note

The minimum of +0 and -0 is -0. The minimum of a QNaN and any value is that value. The minimum of any value and an SNaN is that SNaN converted to a QNaN. FPRF, FR and FI are not modified. If a trap-enabled invalid operation exception occurs, VSR[XT] is not modified. This instruction can be used to operate on single-precision source operands.