lxvl

Load VSX Vector Length

lxvl XT, RA, RB

Loads N bytes into a vector, where N is specified in a GPR.

Details

The lxvl instruction loads a variable-length vector from memory into a VSX register. The length of the data to be loaded is specified by the lower 8 bits of the source general-purpose register RB. If the length is less than 16 bytes, the remaining bytes in the target VSX register are set to zero.

Pseudocode Operation

if TX=0 & MSR.VSX=0 then VSX_Unavailable()
if TX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←(RA=0) ? 0 : GPR[RA]
nb ←EXTZ(GPR[RB].bit[0:7])
if nb>16 then nb ←16
load_data ←0x0000_0000_0000_0000_0000_0000_0000_0000
if MSR.LE = 0 then // Big-Endian byte-ordering
    load_data.byte[0:nb-1] ←MEM(EA,nb)
else // Little-Endian byte-ordering
    load_data.byte[16-nb:15] ←MEM(EA,nb)
VSR[32×TX+T] ←load_data

Programming Note

Loading less than 16 bytes of data using lxvl in BE mode results in data being loaded into the target VSR left-to-right, placing the first byte in the leftmost byte of the target VSR, and padded on the right with 0s. Loading less than 16 bytes of data using lxvl in LE mode results in data being loaded into the target VSR right-to-left, placing the first byte in the rightmost byte of the target VSR, and padded on the left with 0s.

Example

lxvl vs1, r4, r5

Encoding

Binary Layout
0
0
T
1
RA
6
RB
11
TX
21
0
26
0
27
0
28
 
Format XX1-form
Opcode 0x7C00021D
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • RA
    Base
  • RB
    Length Reg