lxvl

Load VSX Vector Length

lxvl XT, RA, RB

Loads N bytes into a vector, where N is specified in a GPR.

Details

Loads up to 16 bytes from memory into a VSX register, with the byte count specified by bits 0–4 of RB. Bytes from address RA|0 (or RA + RB if RA is non-zero) are loaded left-aligned into XT; unloaded bytes are zeroed. This is a VSX category instruction with no effect on condition registers.

Pseudocode Operation

N ← RB[0:4]
if N > 16 then N ← 16
addr ← RA + 0 (if RA != 0 else address from context)
for i ← 0 to N-1
  XT[8*i:8*i+7] ← [addr + i]
for i ← N to 15
  XT[8*i:8*i+7] ← 0

Programming Note

Loading less than 16 bytes of data using lxvl in BE mode results in data being loaded into the target VSR left-to-right, placing the first byte in the leftmost byte of the target VSR, and padded on the right with 0s. Loading less than 16 bytes of data using lxvl in LE mode results in data being loaded into the target VSR right-to-left, placing the first byte in the rightmost byte of the target VSR, and padded on the left with 0s.

Example

lxvl vs1, r4, r5

Encoding

Binary Layout
0
0
T
1
RA
6
RB
11
TX
21
0
26
0
27
0
28
 
Format XX1-form
Opcode 0x7C00021A
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • RA
    Base
  • RB
    Length Reg