pmxvi8ger4

Prefixed Masked VSX Vector Integer 8-bit GER

pmxvi8ger4 AT, XA, XB, XMSK, YMSK

Masked version of 8-bit integer MMA.

Encoding

Binary Layout

PMSK

XMSK

YMSK

Format MMIRR-form

Opcode 0x07900000EC000018

Extension Prefixed

Operands

AT
Accumulator
XA
Src A
XB
Src B
XMSK
Mask A
YMSK
Mask B

Example

pmxvi8ger4 acc0, vs2, vs3, 15, 15

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Prefixed masked version of the 8-bit integer matrix multiply-accumulate (MMA) instruction. Performs a rank-1 update of a 4×4 matrix accumulator using masked 8-bit integer elements, where XMSK controls which columns of XA participate and YMSK controls which rows of XB participate. No condition register or status flags are affected; this is a privileged MMA extension instruction.

Operation

for i in 0..3:
  for j in 0..3:
    if (XMSK[i] == 1) & (YMSK[j] == 1):
      AT[i][j] ← AT[i][j] + (XA[i] × XB[j]) (8-bit signed × 8-bit signed → 32-bit result)

Programming Note

This instruction is useful for performing efficient matrix multiplication on 8-bit signed integers with masking. Ensure that the mask registers (XMSK, YMSK, PMSK) are correctly set to control which elements participate in the accumulation. The operation requires VSX registers, so ensure they are properly aligned and accessible at the privilege level required by your application. Be cautious of potential overflow when accumulating products, as the result is chopped to 32 bits.