stwbrx

Store Word Byte-Reverse Indexed

stwbrx RS, RA, RB

Swaps bytes and stores a word.

Encoding

Binary Layout

31

0:5

RS

6:10

RA

11:15

RB

16:20

662

21:30

/

31

 

Format X-form

Opcode 0x7C00052C

Extension Base

Operands

• RS
  Source
• RA
  Base
• RB
  Index

Example

stwbrx r3, r4, r5

Related

Across architectures

Byte Swap (Endianness Reversal) : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Byte-reverses the low 32 bits of RS and stores the result as a word in memory at address (RA|0) + RB. No status flags are affected. This instruction is used for writing word-sized data in reversed byte order.

Operation

EA ← (RA|0) + RB
[EA] ← byte_reverse_32(RS[32:63])

Programming Note

The stwbrx instruction is useful for storing a word in memory with its byte order reversed, which can be necessary for compatibility with systems that use different endianness. Ensure that the effective address (EA) calculated from registers RA and RB is properly aligned to avoid alignment exceptions. This instruction operates at user privilege level but will raise an exception if the EA is out of bounds or if there are insufficient permissions.