stwci

Store Word Caching Inhibited

stwci RS, RA, RB

Stores a word bypassing the cache.

Details

Store a word from register RS to memory at address (RA + RB), with cache inhibit semantics to bypass the L1 data cache. The word is written directly to L2 or memory. This instruction is used for memory-mapped I/O or device registers where cache bypass is required.

Pseudocode Operation

addr ← (RA) + (RB)
[(addr)] ← (RS)[32:63]
Memory write with cache inhibit attribute

Example

stwci r3, r4, r5

Encoding

Binary Layout
31
0
RS
6
RA
11
RB
16
983
21
/
31
 
Format X-form
Opcode 0x7C0007AF
Extension Base

Operands

  • RS
    Source
  • RA
    Base
  • RB
    Index