stwci

Store Word Caching Inhibited

stwci RS, RA, RB

Stores a word bypassing the cache.

Details

The Store Word Caching Inhibited instruction stores a word bypassing the cache.

Pseudocode Operation

Memory[address] <- r3

Example

stwci r3, r4, r5

Encoding

Binary Layout
31
0
RS
6
RA
11
RB
16
983
21
/
31
 
Format X-form
Opcode 0x7C0007AF
Extension Base

Operands

  • RS
    Source
  • RA
    Base
  • RB
    Index