vmrglw

Vector Merge Low Word

vmrglw vD, vA, vB

Interleaves low-order words.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

396

21:31

 

Format VX-form

Opcode 0x1000018C

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vmrglw vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Merges the two low-order (rightmost) words from vA and vB in an alternating interleaved pattern into vD, with vA word in even position and vB word in odd position. This VMX instruction does not affect any condition or status registers.

Operation

vD[0:31] ← vA[96:127]
vD[32:63] ← vB[96:127]
vD[64:95] ← vA[64:95]
vD[96:127] ← vB[64:95]

Programming Note

The vmrglw instruction is used to merge the low words from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers and requires proper alignment of the input vectors to avoid unexpected results.