vmaxsh

Vector Maximum Signed Halfword

vmaxsh vD, vA, vB

Compares the signed halfwords of two vector registers and stores the maximum values in a third vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

580

21:31

Format VA-form

Opcode 0x10000142

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmaxsh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmaxsh, each pair of corresponding halfwords from VSR[VRA+32] and VSR[VRB+32] are compared. The larger value is stored in the corresponding halfword of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ← VSR[VRA+32].hword[i]
    src2 ← VSR[VRB+32].hword[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].hword[i] ← gt_flag=1 ? src1 : src2
end

Programming Note

This instruction is used to perform element-wise signed halfword maximum operations between two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the halfwords and stores the larger value in the corresponding position of the destination register. Be cautious with alignment as unaligned access might lead to performance penalties or exceptions depending on the system configuration.