divd

Divide Doubleword

divd RT,RA,RB
OE=0 Rc=0

Divides the contents of two registers and places the quotient into a target register.

Details

For divd, the 64-bit dividend is (RA) and the 64-bit divisor is (RB). The 64-bit quotient is placed into register RT. Both operands and the quotient are interpreted as signed integers.

Pseudocode Operation

dividend0:63 ←(RA)
divisor0:63 ←(RB)
RT ←dividend ÷ divisor

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divd r3, r4, r5

// r3 = r4 / r5 (64-bit Signed).

Encoding

Binary Layout
0
0
RT
6
RA
11
RB
16
OE
21
489
22
Rc
31
31
 
Format XO-form
Opcode 0x7C0003D2
Extension Base
Registers Altered CR0, XER

Operands

  • RT
    Target Register (Quotient)
  • RA
    Dividend
  • RB
    Divisor