divd

Divide Doubleword

divd RT,RA,RB

Divides the contents of two registers and places the quotient into a target register.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

489

22:30

Rc

31

 

Format XO-form

Opcode 0x7C0003D2

Extension Base

Operands

• RT
  Target Register (Quotient)
• RA
  Dividend
• RB
  Divisor

Example

divd r3, r4, r5

// r3 = r4 / r5 (64-bit Signed).

Registers Altered

CR0, XER

Related

Across architectures

Integer Divide : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For divd, the 64-bit dividend is (RA) and the 64-bit divisor is (RB). The 64-bit quotient is placed into register RT. Both operands and the quotient are interpreted as signed integers.

Operation

dividend0:63 ←(RA)
divisor0:63 ←(RB)
RT ←dividend ÷ divisor

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.