fctid

Floating Convert with round Double-Precision To Signed Doubleword format X-form (Rc=0)

fctid FRT, FRB

Converts a double-precision floating-point value to a signed 64-bit integer using rounding.

Details

Let src be the double-precision floating-point value in FRB. If src is a NaN, then the result is 0x8000_0000_0000_0000, VXCVI is set to 1, and if src is an SNaN, VXSNAN is set to 1. Otherwise, src is rounded to a floating-point integer using the rounding mode specified by RN. If the rounded value is greater than 263-1, then the result is 0x7FFF_FFFF_FFFF_FFFF and VXCVI is set to 1. Otherwise, if the rounded value is less than -263, then the result is 0x8000_0000_0000_0000 and VXCVI is set to 1. Otherwise, the result is the rounded value converted to 64-bit signed-integer format, and XX is set to 1 if the result is inexact. If an enabled Invalid Operation Exception does not occur, then the result is placed into FRT.

Pseudocode Operation

if src is a NaN then
    FRT <- 0x8000_0000_0000_0000
    VXCVI <- 1
    if src is an SNaN then VXSNAN <- 1
else
    rounded_value <- round(src, RN)
    if rounded_value > 263-1 then
        FRT <- 0x7FFF_FFFF_FFFF_FFFF
        VXCVI <- 1
    else if rounded_value < -263 then
        FRT <- 0x8000_0000_0000_0000
        VXCVI <- 1
    else
        FRT <- convert_to_signed_integer(rounded_value)
        XX <- is_inexact(FRT)
if not enabled Invalid Operation Exception then
    place result into FRT

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.

Example

fctid f1, f3

Encoding

Binary Layout

FRT

FRB

814

Format X-form

Opcode 0xFC00065C

Extension Floating-Point

Registers Altered FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0

Operands

FRT
Target
FRB
Source