xscmpuqp

VSX Scalar Compare Unordered Quad-Precision

xscmpuqp BF, vA, vB

Compares two quad-precision floating-point values and updates the condition register.

Encoding

Binary Layout

0:5

6:8

9:10

11:15

16:20

644

21:30

Format X-form

Opcode 0xFC000508

Extension VSX

Operands

BF
CR Field
vA
Src A
vB
Src B
VRA
Vector Register A
VRB
Vector Register B

Example

xscmpuqp cr0, va, vb

Registers Altered

CR, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction compares the contents of VSR[VRA+32] (src1) and VSR[VRB+32] (src2) in quad-precision format. It sets bits in the CR field BF to indicate the result of the comparison.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ←src1.class.SNaN | src2.class.SNaN
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
CR.bit[4×BF+32] ←FPSCR.FL ←src1 < src2
CR.bit[4×BF+33] ←FPSCR.FG ←src1 > src2
CR.bit[4×BF+34] ←FPSCR.FE ←src1 = src2
CR.bit[4×BF+35] ←FPSCR.FU ←src1.class.SNaN | src1.class.QNaN | src2.class.SNaN | src2.class.QNaN

Programming Note

This instruction is used for comparing two quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious with NaN values, as they can trigger VXSNAN and FU flags in the FPSCR register. The comparison results are stored in the CR register bits corresponding to BF.