vmaxuw

Vector Maximum Unsigned Word

vmaxuw vD, vA, vB

Selects maximum value per word (unsigned).

Encoding

Binary Layout

0:5

6:10

11:15

16:20

132

21:31

Format VA-form

Opcode 0x10000082

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B

Example

vmaxuw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares four unsigned word elements from vA and vB, writing the maximum value of each pair to the corresponding word element in vD. This is a VMX (AltiVec) instruction that operates on all four 32-bit words in parallel with no condition register or status updates.

Operation

vD[0:31] ← max(vA[0:31], vB[0:31])
vD[32:63] ← max(vA[32:63], vB[32:63])
vD[64:95] ← max(vA[64:95], vB[64:95])
vD[96:127] ← max(vA[96:127], vB[96:127])

Programming Note

The vmaxuw instruction is used to perform element-wise comparison of unsigned 32-bit words in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data being processed.