vmodsw

Vector Modulo Signed Word

vmodsw VRT,VRA,VRB

Performs modulo operation on signed integers in vector registers.

Encoding

Binary Layout

4

0:5

VRT

6:10

VRA

11:15

VRB

16:20

1931

21:31

 

Format VX-form

Opcode 0x1000078B

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vmodsw v1, v2, v3

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmodsw, the signed integer in word element i of VSR[VRA+32] is divided by the signed integer in word element i of VSR[VRB+32]. The remainder is placed into word element i of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    dividend ←EXTS(VSR[VRA+32].word[i])
    divisor  ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(dividend % divisor)
end

Programming Note

The vmodsw instruction performs element-wise signed modulo division on vectors. Ensure that the vector registers are properly aligned and that the Vector Facility is enabled (MSR.VEC=1). Be cautious of division by zero, which may result in undefined behavior or exceptions. This operation is typically used in scenarios requiring periodic or cyclic calculations with signed integers.