xscvdphp

VSX Scalar Convert Double to Half-Precision

xscvdphp XT, XB

Converts a double-precision floating-point value to a half-precision floating-point value with rounding.

Details

The xscvdphp instruction converts the double-precision floating-point value in doubleword element 0 of VSR[XB] to a half-precision floating-point value, rounded according to the FPSCR.RN setting. The result is zero-extended and placed into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_flags()
src ← bfp_CONVERT_FROM_BFP64(VSR[BX×32+B].dword[0])
rnd ← bfp_ROUND_TO_BFP16(FPSCR.RN, src)
result ← bfp16_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vex_flag ← FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[TX×32+T].hword[0:2] ← 0x0000_0000_0000
    VSR[TX×32+T].dword[1]   ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP16(result)
end
FPSCR.FR ← (vex_flag=0) & inc_flag
FPSCR.FI ← (vex_flag=0) & xx_flag

Programming Note

['This instruction can be used to operate on a single-precision source operand.', 'Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.']

Example

xscvdphp vs1, vs3

Encoding

Binary Layout
60
0
T
6
17
11
B
16
347
21
BX TX
30 31
 
Format XX2-form
Opcode 0xF0000178
Extension VSX
Registers Altered FPSCR, VSR[TX×32+T].hword[3]

Operands

  • XT
    Target
  • XB
    Source