xvtsqrtdp

Vector Test for software Square Root, Double-Precision

xvtsqrtdp BF,XB

Tests the double-precision floating-point operands in VSR[XB] and sets condition register field BF based on certain conditions.

Encoding

Binary Layout

0:5

6:8

9:31

Format XX2-form

Opcode 0xF00003A8

Extension VSX

Operands

BF
Condition Register Field
XB
Vector-Scalar Register Index

Example

xvtsqrtdp cr0, vs3

Registers Altered

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

This instruction tests each of the two double-precision floating-point elements in VSR[XB] and updates the condition register field BF accordingly. It checks for NaN, infinity, zero, negative values, and denormalized values, setting flags fe_flag and fg_flag based on these conditions.

Operation

if MSR.VSX=0 then
    VSX_Unavailable()

fe_flag ←0b0
fg_flag ←0b0

do i = 0 to 1
    src    ←VSR[32×BX+B].dword[i]
    e_b    ←src.bit[1:11] - 1023
    fe_flag ←fe_flag |
               IsNaN(src) | IsInf(src)  |
               IsZero(src) | IsNeg(src) |
               (e_a <= -970)
    fg_flag ←fg_flag |
               IsInf(src) | IsZero(src) | IsDen(src)
end

fl_flag ←xvrsqrtedp_error() <= 2-14
CR.field[BF] ←0b1 || fg_flag || fe_flag || 0b0

Programming Note

The xvtsqrtdp instruction is used to test double-precision floating-point elements for various conditions like NaN, infinity, zero, negative values, and denormalized values. It updates the condition register (CR) with flags indicating these conditions. Ensure that VSX is enabled in the MSR before using this instruction; otherwise, a VSX_Unavailable exception will occur. The instruction does not require specific alignment for its operands.