xvtdivdp

Vector Test for software Divide Double-Precision

xvtdivdp BF,XA,XB

Performs a double-precision floating-point division on vector elements and sets condition flags based on the results.

Details

The xvtdivdp instruction performs a double-precision floating-point division on each pair of elements from two vector registers, VSR[XA] and VSR[XB], and stores the result in the corresponding element of another vector register, VSR[XT]. It also sets condition flags based on the results of the operation.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

fe_flag ← 0b0
gt_flag ← 0b0
for i = 0 to 1 do
    src1 ← VSR[32×AX+A].dword[i]
    e_a ← src1.bit[1:11] - 1023
    src2 ← VSR[32×BX+B].dword[i]
    e_b ← src2.bit[1:11] - 1023
    fe_flag ← fe_flag |
        IsNaN(src1) | IsInf(src1) |
        IsNaN(src2) | IsInf(src2) |
        IsZero(src2) |
        (e_b <= -1022) |
        (e_b >= 1021) |
        (!IsZero(src1) & ((e_a - e_b) >= 1023)) |
        (!IsZero(src1) & ((e_a - e_b) <= -1021)) |
        (!IsZero(src1) & (e_a <= -970))
    fg_flag ← fg_flag |
        IsInf(src1) | IsInf(src2) |
        IsZero(src2) | IsDen(src2)
end
fl_flag ← xvredp_error() <= 2-14
CR[BF] ← 0b1 || fg_flag || fe_flag || 0b0

Programming Note

The xvtdivdp instruction is used for performing double-precision floating-point division on vector elements. It sets condition flags based on the results, which can be useful for error checking and conditional operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of division by zero and other special cases like NaNs or infinities, as these will set specific condition flags.

Example

xvtdivdp cr0, vs2, vs3

Encoding

Binary Layout

Format XX3-form

Opcode 0xF00003E8

Extension VSX

Registers Altered CR field BF

Operands

BF
Condition Register Field
XA
Index for Source Vector Register A
XB
Index for Source Vector Register B