xvtdivdp

Vector Test for software Divide Double-Precision

xvtdivdp BF,XA,XB

Performs a double-precision floating-point division on vector elements and sets condition flags based on the results.

Details

Tests whether a double-precision floating-point divide operation would be valid for each vector element and sets bits in the specified condition register field accordingly. This VSX instruction compares operands in XA and XB (two double-precision values per 128-bit register) against division validity conditions (divide-by-zero, invalid operands, etc.). The condition register field BF is set to reflect the test results; no other registers are modified.

Pseudocode Operation

for i in 0 to 1 do
  quotient_valid ← test_divide_conditions(XA[i], XB[i])
  CR[BF] ← (quotient_valid, 0, 0, 0)
end for

Programming Note

The xvtdivdp instruction is used for performing double-precision floating-point division on vector elements. It sets condition flags based on the results, which can be useful for error checking and conditional operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of division by zero and other special cases like NaNs or infinities, as these will set specific condition flags.

Example

xvtdivdp cr0, vs2, vs3

Encoding

Binary Layout
18
0
BF
6
XA
16
XB
21
 
Format XX3-form
Opcode 0xF00003E8
Extension VSX
Registers Altered CR field BF

Operands

  • BF
    Condition Register Field
  • XA
    Index for Source Vector Register A
  • XB
    Index for Source Vector Register B