vsl

Vector Shift Left

vsl vD, vA, vB

Shifts the contents of a vector register left by a specified number of bits.

Details

The contents of VSR[VRA+32] are shifted left by the number of bits specified in bits 125:127 of VSR[VRB+32]. Bits shifted out of bit 0 are lost, and zeros are supplied to the vacated bits on the right. The result is placed into VSR[VRT+32], except if, for any byte element in VSR[VRB+32], the low-order 3 bits are not equal to the shift amount, then VSR[VRT+32] is undefined.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
sh ←VSR[VRB+32].bit[125:127]
t ←1
do i = 0 to 14
    t ←t & (VSR[VRB+32].byte[i].bit[5:7] = sh)
end
if t=1 then
    VSR[VRT+32] ←VSR[VRA+32] << sh
else
    VSR[VRT+32] ←UNDEFINED

Programming Note

The vsl instruction shifts the contents of a vector register left by a specified number of bits. Ensure that the shift amount is consistent across all byte elements in the control vector to avoid undefined results. This instruction requires the Vector Facility (MSR.VEC) to be enabled; otherwise, it will raise an exception.

Example

vsl vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
452
 
Format VX-form
Opcode 0x100001C4
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Data
  • vB
    Shift Count
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Shift Amount Vector Register