vmaxsw

Vector Maximum Signed Word

vmaxsw vD, vA, vB

Compares the signed integer values in each word element of two vector registers and stores the larger value into a third vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

644

21:31

Format VA-form

Opcode 0x10000182

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmaxsw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmaxsw, for each integer value i from 0 to 3, the signed integer value in word element i of VSR[VRA+32] is compared to the signed integer value in word element i of VSR[VRB+32]. The larger of the two values is placed into word element i of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].word[i] ← gt_flag=1 ? src1 : src2

Programming Note

The vmaxsw instruction compares each signed word element of two vector registers and stores the maximum value in the destination register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 4-word elements, so input vectors must be properly aligned. Be cautious with signed integer overflow; if both operands are negative and one is closer to zero than the other, the result may not be as expected.