xsnmaddqp

VSX Scalar Negative Multiply-Add Quad-Precision

xsnmaddqp VRT,VRA,VRB
xsnmaddqpo VRT,VRA,VRB

Performs a negative multiply-add operation on quad-precision floating-point values.

Details

The xsnmaddqp instruction multiplies the contents of VSR[VRB+32] and VSR[VRA+32], negates the result, adds it to the contents of VSR[VRT+32], and places the result back into VSR[VRT+32].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ← bfp_CONVERT_FROM_BFP128(VSR[VRT+32])
src3 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[VRT+32] ← result
  FPSCR.FPRF ← fprf_CLASS_BFP128(result)
end
FPSCR.FR ← (vx_flag=0) & inc_flag
FPSCR.FI ← (vx_flag=0) & xx_flag

Programming Note

This instruction is used for performing a scalar negative multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the OX and UX flags in the FPSCR register. The result is rounded according to the rounding mode specified in FPSCR.RN.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction

Example

xsnmaddqp v1, v2, v3

Encoding

Binary Layout
11110001
0
00000000
6
00000000
11
1000
16
 
Format X-form
Opcode 0xFC000388
Extension VSX
Registers Altered FPSCR FPRF FR FI FX VXSNAN VXIMZ VXISI OX UX XX

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register