vextsb2d

Vector Extend Sign Byte To Doubleword

vextsb2d vD, vB

Sign-extends the byte elements of a vector register to doublewords.

Encoding

Binary Layout

0:5

VRT

6:10

11:15

VRB

16:20

1538

21:31

Format VX-form

Opcode 0x10180602

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source
VRT
Target Vector Register
VRB
Source Vector Register

Example

vextsb2d vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vextsb2d, each byte element in VSR[VRB+32] is sign-extended and placed into corresponding doubleword elements in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src ← VSR[VRB+32].dword[i].bit[56:63]
    VSR[VRT+32].dword[i] ← EXTS64(src)
end

Programming Note

This instruction is used to sign-extend each byte in the source vector register into a doubleword in the destination vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes two elements per iteration, and there are no specific alignment requirements for the data. This instruction operates at the user privilege level.