vextractwm

Vector Extract Word Mask

vextractwm RA, vB

Extracts the least significant bit of each word element from a vector register and places them into a general-purpose register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1730

21:31

Format VX-form

Opcode 0x100A0642

Extension VMX (AltiVec)

Operands

RA
Target
vB
Source
RT
Target General Purpose Register
VRB
Source Vector Register

Example

vextractwm r4, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of bit 0 of each word element of VSR[VRB+32] are concatenated and placed into bits 60:63 of GPR[RT]. Bits 0:59 of GPR[RT] are set to 0.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    GPR[RT].bit[60+i] ← VSR[VRB+32].word[i].bit[0]
end
GPR[RT].bit[0:59] ← 0

Programming Note

This instruction is used to extract the least significant bit of each word from a vector register and pack them into the upper four bits of a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The lower 60 bits of the target GPR are always cleared, so be cautious if you need to preserve existing data in those positions.