vbrd

Vector Byte-Reverse Doubleword

vbrd vD, vB

Reverses bytes within each doubleword.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1734

21:31

 

Format VX-form

Opcode 0x100006C6

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source

Example

vbrd vd, vb

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Reverses the byte order within each 64-bit doubleword of the source vector and stores the result in the destination vector. This instruction operates on two doublewords in parallel across the 128-bit vector. No condition flags are affected; this is a VMX/AltiVec instruction.

Operation

vD[0:63] ← vB[56:63] || vB[48:55] || vB[40:47] || vB[32:39] || vB[24:31] || vB[16:23] || vB[8:15] || vB[0:7]
vD[64:127] ← vB[120:127] || vB[112:119] || vB[104:111] || vB[96:103] || vB[88:95] || vB[80:87] || vB[72:79] || vB[64:71]