vaddcuw

Vector Add Carryout Unsigned Word

vaddcuw vD, vA, vB

Adds the contents of two vector registers and writes the carry-out to another vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

384

21:31

Format VX-form

Opcode 0x10000180

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vaddcuw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vaddcuw, the sum of the unsigned integer values in word elements of VSR[VRA+32] and VSR[VRB+32] is placed into word elements of VSR[VRT+32]. The carry out of the 32-bit sum is zero-extended to 32 bits and placed into word element i of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32((src1 + src2) >> 32)
end

Programming Note

This instruction is used for adding unsigned integers in vector registers, with the carry out being zero-extended and stored alongside the result. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes each word element independently, so alignment of data within the vectors is not strictly required.