drrndq

Decimal Reround Quad-Precision

drrndq vD, vA, vB

Rerounds a 128-bit DFP number to fewer digits.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:30

Format X-form

Opcode 0xFC000046

Extension Decimal Floating-Point

Operands

vD
Target
vA
Source
vB
Control

Example

drrndq vd, va, vb

Registers Altered

FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Rerounds a 128-bit decimal floating-point number in vA to a precision specified by control information in vB, storing the result in vD. This operation reduces the number of significant digits while adjusting the exponent accordingly. Rounding uses the mode specified in FPSCR[RN]. The instruction is part of the Decimal Floating-Point extension.

Operation

vD ← ReroundDFP128(vA, vB, FPSCR[RN])

Programming Note

The drrndq instruction is used for precise decimal arithmetic operations, particularly useful in financial applications where exact decimal representation is crucial. Ensure that the source operands (FRA and FRB) are correctly aligned and formatted as quad-precision decimals to avoid precision loss. The rounding mode control (RMC) should be set according to the desired rounding behavior, such as round-to-nearest or truncate. This instruction operates at a privilege level that allows access to floating-point operations, and it may raise exceptions if operands are out of range or if there are invalid operations.