xscvqpuwz

VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format

xscvqpuwz VRT,VRB

Converts a quad-precision floating-point value to an unsigned word format.

Details

The xscvqpuwz instruction converts the quad-precision floating-point value in VSR[VRB+32] to a 32-bit unsigned integer format and places the result into the target VSR[VRT+32]. The conversion follows specific rules based on the range of the source value.

Pseudocode Operation

if src is a QNaN then
    fr(0)
    fi(0)
    fx(VXCVI)
    error()
else if src is a SNaN then
    fr(0)
    fi(0)
    fx(VXCVI)
    fx(VXSNAN)
    error()
elsif src ≤ Nmin-1 then
    T(Nmin)
    fr(0)
    fi(0)
    fprf(0bUUUUU)
    fx(VXCVI)
else if Nmin-1 < src < Nmin then
    T(Nmin)
    fr(0)
    fi(1)
    fprf(0bUUUUU)
    fx(XX)
    error()
elsif src = Nmin then
    T(Nmin)
    fr(0)
    fi(0)
    fprf(0bUUUUU)
else if Nmax < src < Nmax+1 then
    T(Nmax)
    fr(0)
    fi(1)
    fprf(0bUUUUU)
    fx(XX)
    error()
elsif src = Nmax then
    T(Nmax)
    fr(0)
    fi(0)
    fprf(0bUUUUU)
else if src ≥ Nmax+1 then
    fr(0)
    fi(0)
    fx(VXCVI)
    error()
else
    T(f2i(trunc(src)))
    fr(0)
    fi(0)
    fprf(0bUUUUU)
end if

Programming Note

This instruction is used to convert a quad-precision floating-point number to an unsigned 32-bit integer, rounding towards zero. Be cautious with NaN and out-of-range values, as they can trigger exceptions and set specific flags in the FPSCR register. Ensure that the source vector register (VRB+32) contains a valid quad-precision value to avoid unexpected behavior.

Example

xscvqpuwz v1, v3

Encoding

Binary Layout
63
0
FRT
6
1
11
FRB
16
836
21
Rc
31
 
Format X-form
Opcode 0xFC010688
Extension VSX
Registers Altered FPSCR.FR, FPSCR.FI, FPSCR.FPRF, FPSCR.FX

Operands

  • VRT
    Target Vector-Scalar Register
  • VRB
    Source Vector-Scalar Register