xscvqpuwz

VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format

xscvqpuwz VRT,VRB

Converts a quad-precision floating-point value to an unsigned word format.

Encoding

Binary Layout

63

0:5

FRT

6:10

1

11:15

FRB

16:20

836

21:30

Rc

31

 

Format X-form

Opcode 0xFC010688

Extension VSX

Operands

• VRT
  Target Vector-Scalar Register
• VRB
  Source Vector-Scalar Register

Example

xscvqpuwz v1, v3

Registers Altered

FPSCR.FR, FPSCR.FI, FPSCR.FPRF, FPSCR.FX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts a quad-precision floating-point value from the source VSR to an unsigned 32-bit word integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Out-of-range or negative values saturate; FPSCR status is updated with conversion exception flags.

Operation

VRT[0:31] ← ConvertToUnsignedWord_RoundTowardZero(VRB[0:127])
VRT[32:127] ← 0

Programming Note

This instruction is used to convert a quad-precision floating-point number to an unsigned 32-bit integer, rounding towards zero. Be cautious with NaN and out-of-range values, as they can trigger exceptions and set specific flags in the FPSCR register. Ensure that the source vector register (VRB+32) contains a valid quad-precision value to avoid unexpected behavior.