xvdivsp

VSX Vector Divide Single-Precision

xvdivsp XT, XA, XB

Divides the contents of two vector registers and places the result in another vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:31

Format XX3-form

Opcode 0xF00002C0

Extension VSX

Operands

XT
Target
XA
Src A
XB
Src B
VD
Destination Vector Register
VA
Source Vector Register (Dividend)
VB
Source Vector Register (Divisor)

Example

xvdivsp vs1, vs2, vs3

Registers Altered

FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xvdivsp, each element of the source vectors VSR[XA] and VSR[XB] is divided to produce a quotient that is placed into the corresponding element of the target vector VSR[XT].

Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    v    ←bfp_DIVIDE(src1,src2)
    rnd  ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxidi_flag=1 then SetFX(FPSCR.VXIDI)
    if vxisi_flag=1 then SetFX(FPSCR.VXZDZ)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)
    if zx_flag=1 then SetFX(FPSCR.ZX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) 
                       | (FPSCR.VE & vxidi_flag) 
                       | (FPSCR.VE & vxzdz_flag) 
                       | (FPSCR.OE & ox_flag) 
                       | (FPSCR.UE & ux_flag) 
                       | (FPSCR.ZE & zx_flag) 
                       | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

The xvdivsp instruction performs element-wise division of single-precision floating-point numbers in VSX vectors. Ensure that the VSX facility is enabled (MSR.VSX=1) to avoid exceptions. Handle potential exceptions by checking the FPSCR flags, especially VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, and XX. Be cautious of alignment requirements for vector registers to maintain performance.