tlbie

Translation Lookaside Buffer Invalidate Entry

tlbie RB, RS

Invalidates a TLB entry corresponding to the address in RB.

Details

The tlbie instruction is used to invalidate a TLB entry. The parameters describe the type of translations to invalidate and the scope of the invalidation.

Pseudocode Operation

IS ← (RB)52:53
if MSRHV=1 then search_LPID=RS32:63 else search_LPID=LPIDRLPID
switch(IS)
    case (0b00):
        if RIC=0
            if effR=0 then
                L ← (RB)63
                if L = 0 then inst_AVA = (RB)0:51 else inst_AVA = (RB)0:43||(RB)56:62||0b0
                sg_size ← segment size specified in (RB)54:55
                for each thread
                    for each TLB entry
                        entry_scope = number of bytes of VA space translated by TLB entry
                        es ← log_base_2(entry_scope)
                        i = 63-es
                        if (entry_VA14:i+14 = inst_AVA0:i) & (entry_sg_size = sg_size) & (entry_LPID = search_LPID) & (entry_process_scoped = 0) then TLB entry ← invalid
            else # effR̸=0
                actual_pg_size = page size specified in (RB)56:58
                p ← log_base_2(actual_pg_size)
                i = 63-p
                for each thread
                    for each TLB entry
                        if (entry_EA0:i = (RB)0:i) & (entry_actual_pg_size = actual_pg_size) & (entry_LPID = search_LPID) & (entry_process_scoped = PRS) & ((PRS = 0) | (entry_PID = (RS)0:31)) then TLB entry ← invalid
        else if RIC=3 then
            sg_size ← segment size specified in (RB)54:55
            pg_size ← f(GS)
            number_of_pgs ← g(GS)
            p ← log_base_2(pg_size)
            n ← log_base_2(number_of_pgs)
            i ← 63-p
            va14:14+i ← (RB)0:i-n || n0
            do j=n0 to n1    # j=0 to 2n-1, in binary
                for each thread
                    for each TLB entry
                        if (entry_VA14:14+i = (va14:14+i+j)) & (entry_sg_size = sg_size) & (entry_scope = pg_size) & (entry_LPID = search_LPID) & (entry_process_scoped = 0) then TLB entry ← invalid
    case (0b01):
        if RIC=0 | RIC=2 then
            for each TLB entry for each thread
                if (entry_LPID=search_LPID) & (entry_PID=RS0:31) & (entry_PRS=1)

Programming Note

The use of effR in the RTL and verbal descriptions of tlbie[l] beginning in Version 3.1B of the architecture is a clarification of earlier architecture, not a functional change.

Example

tlbie r3, r4

Encoding

Binary Layout
0
0
RS
6
6
30
11
31
RIC
PRS
R
RB
 
Format X-form
Opcode 0x7C000264
Extension Privileged
Registers Altered MSR

Operands

  • RB
    Effective Address
  • RS
    Process ID (PID)
  • RIC
    Radix Invalidation Control
  • PRS
    Process Scoped
  • effR
    Effective R
  • R
    Effective R bit indicating whether to use the effective address or segment/page size information.