tlbie

Translation Lookaside Buffer Invalidate Entry

tlbie RB, RS

Invalidates a TLB entry corresponding to the address in RB.

Encoding

Binary Layout
0
0:5
RS
6:8
6
9
11
10
RIC
11:15
PRS
16:20
R
21:30
RB
31
 
Format X-form
Opcode 0x7C000264
Extension Privileged

Operands

  • RB
    Effective Address
  • RS
    Process ID (PID)
  • RIC
    Radix Invalidation Control
  • PRS
    Process Scoped
  • effR
    Effective R
  • R
    Effective R bit indicating whether to use the effective address or segment/page size information.

Example

tlbie r3, r4

// Flush page translation.

Registers Altered

MSR

Related

More in Privileged

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Invalidates a translation lookaside buffer (TLB) entry corresponding to the effective address in RB. This privileged instruction allows selective invalidation controlled by the RIC (Radix Invalidation Control), PRS (Process Scoped), and R fields. The RS operand may contain a Process ID for process-scoped invalidations in radix MMU implementations. This instruction affects only the TLB state and does not modify condition or status registers.

Operation

Invalidate TLB entry(ies) corresponding to address in RB, process ID in RS, controlled by RIC, PRS, and R fields; synchronization semantics depend on the radix MMU configuration.

Programming Note

The use of effR in the RTL and verbal descriptions of tlbie[l] beginning in Version 3.1B of the architecture is a clarification of earlier architecture, not a functional change.