vcmpbfp

Vector Compare Bounds Floating-Point

vcmpbfp VRT,VRA,VRB

Compares two VSRs word element by word and sets the target VSR if Rc=1.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

966

22:31

Format VC-form

Opcode 0x100003C6

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpbfp v1, v2, v3

Registers Altered

CR6

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a bounds check comparing each of four 32-bit floating-point elements in VRA against the range defined by two bounds in VRB. The result is stored in VRT as a 4-bit value per element indicating which bound(s) the value violates. When the Rc bit is set (vcmpbfp.), the CR6 field is updated based on the result.

Operation

for i in 0 to 3:
  if isnan(VRA[32*i:32*i+31]) or isnan(VRB[32*i:32*i+31]) then
    VRT[30*i:30*i+29] ← 0b11
  else if VRA[32*i:32*i+31] < -VRB[32*i:32*i+31] then
    VRT[30*i:30*i+29] ← 0b10
  else if VRA[32*i:32*i+31] > VRB[32*i:32*i+31] then
    VRT[30*i:30*i+29] ← 0b01
  else
    VRT[30*i:30*i+29] ← 0b00
if Rc = 1 then
  CR6 ← 0b0001 if all results are within bounds else 0b0000

Programming Note

Each single-precision floating-point value in VSR[VRB+32] should be non-negative; if it is negative, the corresponding element in VSR[VRA+32] will necessarily be out of bounds. One exception to this is when the value of an element in VSR[VRB+32] is -0.0 and the value of the corresponding element in VSR[VRA+32] is either +0.0 or -0.0. +0.0 and -0.0 compare equal to -0.0.