vandc

Vector AND with Complement

vandc vD, vA, vB

Bitwise AND of vA with the ones' complement of vB (vA & ~vB).

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1092

21:31

 

Format VX-form

Opcode 0x10000444

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vandc vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a bitwise AND of vA with the ones' complement of vB, effectively computing vA & ~vB, and stores the result in vD. Each bit is set in the result only if it is set in vA and clear in vB. No status flags are affected.

Operation

vD ← vA & ~vB

Programming Note

The vandc instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception. Ensure that the MSR.VEC bit is set before using this instruction. This operation is useful for masking bits where you want to retain certain bits while complementing others.