vandc

Vector AND with Complement

vandc vD, vA, vB

Bitwise AND of vA with the ones' complement of vB (vA & ~vB).

Details

The Vector AND with Complement (vandc) instruction performs a bitwise AND operation between the contents of VSR[VRA+32] and the complement of the contents of VSR[VRB+32]. The result is then stored in VSR[VRT+32]. If the Vector Facility is not available, it raises an exception.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
VSR[VRT+32] ←VSR[VRA+32] & ¬VSR[VRB+32]

Programming Note

The vandc instruction requires the Vector Facility to be enabled; otherwise, it will raise an exception. Ensure that the MSR.VEC bit is set before using this instruction. This operation is useful for masking bits where you want to retain certain bits while complementing others.

Example

vandc vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1092
21
 
Format VX-form
Opcode 0x10000444
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B