vgbbd

Vector Gather Bits by Bytes by Doubleword

vgbbd vD, vB

The contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32].

Encoding

Binary Layout

Format VX-form

Opcode 0x1000050C

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source
VRT
Target Vector Register
VRB
Source Vector Register

Example

vgbbd vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vgbbd, the contents of bit j of each byte of doubleword element i of VSR[VRB+32] are concatenated and placed into byte j of doubleword element i of VSR[VRT+32]. An 8-bit × 8-bit bit-matrix transpose is performed on the contents of each doubleword element of VSR[VRB+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    do j = 0 to 7
        do k = 0 to 7
            b ← VSR[VRB+32].dword[i].byte[k].bit[j]
            VSR[VRT+32].dword[i].byte[j].bit[k] ← b
        end
    end
end

Programming Note

The vgbbd instruction performs a bit-matrix transpose on each doubleword element of the source vector, effectively rotating bits within bytes. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This operation requires aligned access to the vector registers. Be cautious with privilege levels; this instruction may require supervisor or hypervisor mode depending on system configuration.