vmodsd

Vector Modulo Signed Doubleword

vmodsd VRT,VRA,VRB

Performs vector modulo signed doubleword operation.

Encoding

Binary Layout

4

0:5

VRT

6:10

VRA

11:15

VRB

16:31

 

Format VX-form

Opcode 0x100007CB

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vmodsd v1, v2, v3

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmodsd, each integer value i from 0 to 1, the signed integer in doubleword element i of VSR[VRA+32] is divided by the signed integer in doubleword element i of VSR[VRB+32]. The remainder is placed into doubleword element i of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    dividend ←EXTS(VSR[VRA+32].dword[i])
    divisor  ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(dividend % divisor)
end

Programming Note

The vmodsd instruction performs element-wise signed modulo division on doublewords. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid a Vector_Unavailable exception. Handle potential division by zero, as it will result in an undefined remainder. The operation is performed on elements 0 and 1 of the specified vector registers.