xsnmsubadp

VSX Scalar Negative Multiply-Subtract Type-A Double-Precision

xsnmsubadp XT,XA,XB

Performs a negative multiply-subtract operation on double-precision floating-point values.

Details

For xsnmsubadp, the double-precision floating-point value in doubleword element 0 of VSR[XA] is multiplied by the double-precision floating-point value in doubleword element 0 of VSR[XT], and the result is added to the negated double-precision floating-point value in doubleword element 0 of VSR[XB]. The final result is normalized, rounded to double-precision using the rounding mode specified by RN, and placed into doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to 0.

Pseudocode Operation

if 'xsnmsubadp' then do
    src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
    src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[0])
    src3 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
end
v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v))
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vximz_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Programming Note

This instruction is commonly used in applications requiring complex floating-point arithmetic, such as scientific computations and simulations. Ensure that the input values are properly aligned to avoid precision loss. The instruction operates at the user privilege level and may raise exceptions if invalid operations occur, such as division by zero or overflow. Performance can be optimized by ensuring that the VSX registers are preloaded with the necessary data.

Example

xsnmsubadp vs1, vs2, vs3

Encoding

Binary Layout
0
0
6
6
11
11
16
16
21
21
29
29
30
30
31
31
 
Format XX3-form
Opcode 0xF0000588
Extension VSX
Registers Altered FPSCR, VSR[XT]

Operands

  • XT
    Target Vector-Specific Register
  • XA
    Source Vector-Specific Register
  • XB
    Source Vector-Specific Register