vupkhsh

Vector Unpack High Signed Halfword

vupkhsh vD, vB

Unpacks the high signed halfwords from a vector register into a new vector register.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

590

21:31

 

Format VX-form

Opcode 0x1000024E

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vupkhsh vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction unpacks the high signed halfwords from VSR[VRB+32] and places them into VSR[VRT+32]. Each halfword is sign-extended to form a word.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
for each integer value i from 0 to 3 do
    VSR[VRT+32].word[i] ←EXTS32(VSR[VRB+32].hword[i])

Programming Note

This instruction is used to extract the high signed halfwords from a vector register and sign-extend them into another vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes each of the four halfwords in the source register, so ensure proper alignment if dealing with specific data structures.