vsubuqm

Vector Subtract Unsigned Quadword Modulo

vsubuqm vD, vA, vB

Subtracts the contents of two vector registers and places the result in another vector register, modulo operation.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1280

21:31

 

Format VA-form

Opcode 0x10000500

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vsubuqm vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsubuqm, the unsigned quadword subtraction of the contents of VSR[VRA+32] and the one's complement of VSR[VRB+32], plus 1, is placed into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(¬VSR[VRB+32])
VSR[VRT+32] ←CHOP128(src1 + src2 + 1)

Programming Note

This instruction performs an unsigned quadword subtraction modulo operation. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious with alignment as it may affect performance or cause exceptions if not properly aligned. The result is placed in the destination vector register, and developers should handle potential overflow conditions appropriately.