vmuleuw

Vector Multiply Even Unsigned Word

vmuleuw vD, vA, vB

Multiplies the even-numbered words of two vector registers and places the results in a destination vector register.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

136

21:31

 

Format VX-form

Opcode 0x10000288

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vmuleuw vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmuleuw, each pair of even-numbered words from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the results are placed into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTZ(VSR[VRA+32].word[2×i])
    src2 ←EXTZ(VSR[VRB+32].word[2×i])
    VSR[VRT+32].dword[i] ←CHOP64(src1 × src2)
end

Programming Note

This instruction multiplies even-numbered words from two vector registers and stores the results in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as the multiplication result is truncated to 64 bits before storage.