dcblc

Data Cache Block Lock Clear

dcblc CT, RA, RB

Clears a cache line lock.

Encoding

Binary Layout

31

0:5

CT

6:10

RA

11:15

RB

16:20

390

21:30

/

31

 

Format X-form

Opcode 0x7C00030C

Extension Embedded

Operands

• CT
  Cache Target
• RA
  Base
• RB
  Index

Example

dcblc 0, r4, r5

Related

More in Embedded

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Clears the lock bit associated with the cache line at the address formed by adding RA and RB. The CT field specifies the cache target (L1, L2, etc.). This embedded instruction is typically used in multiprocessor environments to release a previously locked cache line. No condition flags are affected.

Operation

EA ← (RA) + (RB)
ClearCacheLock(CT, EA)