creqv
Condition Register Equivalent
creqv CRb,CRA,CRB
Sets the condition register field to 1 if the corresponding fields of two source registers are equal, otherwise sets it to 0.
Encoding
Binary Layout
010011
0:5
CRb
6:10
CRA
11:15
CRB
16:18
01001
19:20
00001
21:30
Rc
31
Operands
-
CRb
Target Condition Register Field -
CRA
Source Condition Register Field -
CRB
Source Condition Register Field
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
Performs a bitwise equivalence operation on two condition register fields and places the result in the target condition register field (setting the target bit to 1 if both source bits are equal, 0 otherwise). This Base category instruction operates entirely within the condition register and does not affect other status fields. It is commonly used in conditional branch logic and CR field manipulation.
Operation
CR[CRb] ← CR[CRA] XNOR CR[CRB]
CR[CRb] ← (CR[CRA] AND CR[CRB]) OR (NOT CR[CRA] AND NOT CR[CRB])Programming Note
The creqv instruction is useful for comparing two condition register fields and determining where they are equivalent. It's important to ensure that the source registers (CRA and CRB) are correctly set before using this instruction, as incorrect values can lead to unexpected results in subsequent conditional logic. This instruction operates at the user privilege level and does not generate exceptions under normal circumstances.