vmul10euq

Vector Multiply-by-10 Extended Unsigned Quadword

vmul10euq VRT,VRA,VRB

Multiplies the contents of two vector registers by 10 and extends the result.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:31

Format VX-form

Opcode 0x10000241

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmul10euq v1, v2, v3

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction multiplies the unsigned integer value in VSR[VRA+32] by 10, adds the unsigned packed decimal value from bits 124:127 of VSR[VRB+32], and places the rightmost 128 bits of the result into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src ← EXTZ(VSR[VRA+32])
cin ← EXTZ(VSR[VRB+32].bit[124:127])
prod ← (src << 3) + (src << 1) + cin
VSR[VRT+32] ← CHOP128(prod)

Programming Note

This instruction is used for multiplying an unsigned integer by 10 and adding a packed decimal value. Ensure that the Vector Facility is enabled in the MSR register to avoid exceptions. The operation requires proper alignment of input values, specifically focusing on bits 124:127 of the second source vector. Be cautious with overflow conditions as the result is truncated to 128 bits.